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MAC/PHY(MII/RMII/GMII/RGMII)基本介绍

2023-01-31
David


参考 1. 以太网详解(一)-MAC/PHY/MII/RMII/GMII/RGMII基本介绍(转)

2. MII、GMII、RMII、RGMII、SGMII、XGMII

3. USXGMII是什么?

释义

interface name transfer data lines signal
MII media independant interface 4根 TX_CLK/TX_ER/TX_EN/TXD[3:0]/
RX_CLK/RX_ER/RX_DV/RXD[3:0]/
CRS/COL/
MDC/MDIO
RMII reduced MII 并行,2根 REF_CLK(50MHz)/
TX_EN/TXD[1:0]/
RX_EN/RXD[1:0]/
CRS_DV/
MDC/MDIO
SMII Serial MII 串行 REF_CLK(125MHz)/
TXD/RXD/
SYNC/
MDC/MDIO
GMII Gigabit MII 并行,8根 GTX_CLK/
TX_CLK/TX_ER/TX_EN/TX[7:0]/
RX_CLK/RX_DV/RX_ER/RX[7:0]/
CRS/COL/
MDC/MDIO
RGMII reduced Gigabit MII 并行,4根 TX_CLK(125MHz)/TX_CTL/TXD[3:0]/
RX_CLK(125MHz)/RX_CTL/RXD[3:0]/
MDC/MDIO
SGMII Serial Gigabit MII 串行  
XGMII X-对应罗马数字10,10GMII速    

以图释义 CPU-MAC-PHY block CPU-MAC-PHY internal CPU-MAC-PHY MAC internal CPU-MAC-PHY PHY internal


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